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. Author manuscript; available in PMC: 2011 Jun 22.
Published in final edited form as: Dig Tech Pap IEEE Int Solid State Circuits Conf. 2010;2010:120–121. doi: 10.1109/ISSCC.2010.5434028

Figure 6.4.3.

Figure 6.4.3

Neural signal-flow diagram, emphasizing the VCO architecture and on-chip class-AB PA, which reduces the effects of loading on the VCO. Inset: Wirelessly recorded 32ch waveforms when the WINeR-6 ASIC is inductively powered.