Table 2. Hardware utilization statistics.

	MC	MH	pI	μH	Complete System
Flip Flops	444 (2%)	704 (3%)	1,037 (4%)	1,518 (6%)	3,703 (13%)
Look-up Tables	1,224 (4%)	1,935 (7%)	2,857 (10%)	4,183 (15%)	10,202 (37%)
Slices	711 (5%)	1,125 (8%)	1,685 (12%)	2,428 (18%)	5,923 (43%)
Gates	105,640	167,263	246,492	360,935	880,329
Block RAMs	-	-	2 (1%)	11 (8%)	13 (10%)
MULT18×18s	-	-	1 (1%)	10 (7%)	11 (8%)
Max Clock Frequency	75.34 Mhz	75.30 Mhz	73.04 Mhz	67.51 MHz	55.16 Mhz

The table reports the resources used by the 4 codes (MC, MH, pI, μH) used to predict SCAPs when implemented on a Xilinx Virtex II PRO family FPGA board.