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. Author manuscript; available in PMC: 2011 Jul 25.
Published in final edited form as: J Parallel Distrib Comput. 2008 Oct;68(10):1307–1318. doi: 10.1016/j.jpdc.2008.05.013

Table 1.

CUDA 1.0 vs CUDA 1.1. The Registers column refers to registers per thread.

FHd Reconstruction (All times in min:sec)
CUDA 1.0 CUDA 1.1 CUDA 1.0 CUDA 1.1
Config Registers GFLOPS Registers GFLOPS FhD Solver Total FhD Solver Total
GPU.Base 14 7.02 18 7.05 53:51 0:25 54:17 53:36 0:17 53:53
GPU.RegAlloc 16 11.07 20 11.07 34:08 0:25 34:33 34:09 0:17 34:27
GPU.Layout 16 13.10 20 12.85 28:51 0:25 29:16 29:25 0:17 29:42
GPU.ConstMem 15 85.82 19 82.79 4:24 0:25 4:50 4:34 0:18 4:52
GPU.FastTrig 13 127.54 13 125.49 1:10 0:25 1:36 1:11 0:17 1:29
GPU.Tune 19 151.45 13 184.40 0:59 0:25 1:25 0:49 0:17 1:06
GPU.Multi 19 502.22 13 615.75 0:18 0:25 0:43 0:15 0:18 0:32