Table 1.

Times associated with the Internal Pipeline of Figure 4.

Time (s)	Description
T1 = 17 ·TCLK_CMOS	Latency from giving the signal to shoot a new image with null exposure time.
T2 = 134 · TCLK_CMOS	Time to write one row in FIFO buffer.
T3 = 4 ·TCLK_CMOS	Latency before decimation.
$T_4=\left(\frac{\mathit{ROW\_SIZE}}{D}\right)\cdot T_{\mathit{CLK\_CMOS}}$	Time to decimate one row
T5 = (BURST_SIZE + 23) · TCLK_CMOS	Time to package one burst in FIFO buffer.
T6 = ((BURST_SIZE + 255) · TCLK_SYS) + ΔT6	Time to write one pixel burst into memory.
T7 = ((BURST_SIZE + 255) · TCLK_SYS) + ΔT7	Time to read one pixel burst in memory
T8 = f (hw_proc)	HW processing time of one pixel burst.
T9	Memory access time between HW processing of pixel bursts. Includes memory access latency.
T10 = f (sw_proc)	SW processing time of one pixel burst loaded in Cache Memory.
T11	Memory access time to update one pixel burst for SW processing in Cache Memory

where:

• T_{CLK_CMOS:} CMOS controller clock signal period (f_{CLK_CMOS} = 66 MHz).
• T_{CLK_SYS}: clock signal period of the architecture’s internal buses (f_{CLK_SYS} = 100 MHz).
• ROW_SIZE: number of pixels per column in the CMOS sensor (1,280 pixels).
• COL_SIZE: number of pixels per row in the CMOS sensor (1,024 pixels).
• D: decimation factor (1 to 10).
• BURST_SIZE: number of words for access memory with a pixel burst.
• N: number of bytes per word of the memory data write bus (4 bytes/word).
• ΔT6: memory write latency.
• ΔT7: memory read latency.