Table 3.
User timing constraints for the developed design.
| HW Component | Clock | Maximum Frequency (MHz) | Required Frequency (MHz) |
|---|---|---|---|
| PPC405 | DPLB0_PLB_Clk DPLB1_PLB_Clk IPLB0_PLB_Clk |
209.266 346.663 287.965 |
100 100 100 |
| IPLB1_PLB_Clk | 287.965 | 100 | |
| PLB_SLAVES | PLB_Clk | 258.522 | 100 |
| BRAM | BRAM_Clk | 250.240 | 100 |
| RS232 | SPLB_Clk | 218.948 | 100 |
| LEDS | SPLB_Clk | 343.536 | 100 |
| SWITCHES | SPLB_Clk | 343.536 | 100 |
| FLASH | MCH_PLB_Clk | 174.497 | 100 |
| INT_CTRL | SPLB_Clk | 265.555 | 100 |
| DDR_SDRAM | PLB_Clk | 369.399 | 100 |
| PLB_CMOS_SENSOR | sysclk | 150.115 | 60 |
| MPLB_Clk | 195.792 | 100 | |
| SPLB_Clk | 151.357 | 100 | |
| ETHERNET_MAC | SPLB_Clk | 149.157 | 100 |
| PHY_tx_clk | 396.873 | 100 | |
| PHY_rx_clk | 305.446 | 100 | |
| PLB_HW_IMAGE_PROCESSING | SPLB_Clk | 156.777 | 100 |
| MPLB_Clk | 200.906 | 100 |