Table 1.
Comparison of Different Implementations.
| Hardware based on | Complexity | Scanning Time(ms)@Nr of bits of A/D conversion | Average Power Consumption with/without reading a row | Cost of the main IC ($) | Hardware Resources | ||||
|---|---|---|---|---|---|---|---|---|---|
| Nr. of ICs | Nr. of PCB layers | Size of the array M × N | Absolute | Relative to array size | Absolute | Relative to array size | |||
| PIC18F4680 (L) | 10 | 2 | 16 × 16 (256) | 15.6 (10 b) | 0.975/row | 37 mA@5 V/25 mA@5 V | 0.72 mW/tactel | 6.32 | CPU 18PIC@40 MHz, 3.3 Kb SRAM, 64 Kb FLASH, 1 8 × 8 Multiplier ALU, 36 digital I/O, 8.5 mA@IOL 0.6 V@VOL, 11 input analog A/D channels, Up to 10 bits A/D converter, UART, SPI, I2C, CAN facilities |
| PIC18F4680 (M) | 5 | 2 | 11 × 19 (201) | 10* (10b) | 0.515*/row | NA | NA | ||
| PSoC CY8C29466 |
1 | 2 | 14 × 4 (56) | 31.8 (8 b) 7.2 (7 b) 1.36 (5 b) | 2.27/row (8b) 0.51/row (7b) 0.10/row(5b) | 37.7 mA@5 V/20 mA @5 V | 3.36 mW/tactel | 8.02 | CPU Core M8C@24 MHz, 2 Kb SRAM, 32 Kb FLASH, 2 8 × 8 Multiplier ALU 24 digital I/O, 12 Analog I @24 mA sink, 4 Analog O @30 mA 12 analog blocks, 8 digital blocks Up to 14 bits A/D converters UART, SPI, I2C facilities |
| FPGA PI SPARTAN 3AN-50 |
1 | 4 | 8 × 8 (64) | 4*(8b) | 0.5*/row | NA | NA | 8.94 | 50 MHz, 50 K System Gates, 176 Configurable Logic Blocks, 3 18 × 18 dedicated multipliers, 11 Kbits Distributed RAM, 54 Kbits Block RAM, 1 Mbit FLASH, 108 I/O pins @ 24 mA IOH VOH |
| FPGA AI SPARTAN 3AN-50 |
5 | 4 | 16 × 16 (256) | 5.5 (8b) | 0.343/row | 100 mA@3.3 V/60 mA@3.3 V | 1.3 mW/tactel | ||