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. Author manuscript; available in PMC: 2012 Jan 1.
Published in final edited form as: IEEE Trans Circuits Syst I Regul Pap. 2011;58(8):1749–1760. doi: 10.1109/TCSI.2010.2103172

Fig. 9.

Fig. 9

Simulated power consumption of the comparator versus VREC showing power overheads for employing the offset-control functions (fc = 13.56 MHz, RL = 500 Ω, and CL = 10 μF). Curve (a) shows the total power consumption of the high speed comparator, (b) is the power consumption of the CG comparator and CS inverters, and (c) indicates the consumption of the offset-control blocks.