Power voltage current convertor using quasi complementary MOSFET current mirrors

Abstract

A voltage current convertor is described having a quasi complementary class AB architecture that is particularly suited to implementation using discrete power MOSFETs. High-voltage mirror designs are presented, enabling the construction of sources with kilovolt compliance range, tens of watts of output power and greater than 100 kHz bandwidth. GΩ output impedance and distortion below 1% can be obtained with no trimming or transistor matching.

Introduction

Voltage-current convertors (VCCS) with high output compliance voltages have a number of applications, notably the driving of piezoelectric actuators [1]. An obvious approach to power current source implementation is to apply a power operational amplifier (OA) [2]. Although convenient, performance is limited by the bandwidth and common mode rejection of the high-voltage OA. Furthermore, an OA is designed for a low output impedance, so this approach forgoes the high output impedance that is easily achieved by taking the output from the collector or drain of the output devices. Alternatively, as in [1], a discrete power stage may be used to boost the output capabilities of a conventional OA. In either case, this commonly involves measuring the output current by the voltage drop across a relatively small sense resistance, and relying on overall feedback and the OA gain to bootstrap this into a high output impedance. If the load must be grounded, then this output current must be measured at a floating high-impedance node, which creates considerable difficulties.

An alternate VCCS architecture (Fig. 1a) avoids this problem by using the OA supply terminals to control current mirrors referenced to each supply rail, summing these currents at the output [3]. There is no overall feedback.

Fig. 1.

a. Supply current mirroring VCCS b. Quasi-complementary VCCS with current gain (composite of Figs. 2, 3, 4).

Quasi-complementary VCCS

Fig. 1b shows the proposed quasi-complementary VCCS that uses two N-type power mirrors configured to give a 1:n current gain in the output stage. One mirror is referenced to the output, so both the I_REF and I_OUT currents flow into the output, requiring a 1:n-1 ratio. The advantage of the quasi-complementary structure is that power N-MOSFETs are available at higher output voltages and have lower output capacitances than complementary P-channel devices.

N-type ratioed power mirror

Fig. 2 shows the proposed N-type mirror with a 1:10 current ratio between I_REF and I_OUT. The use of a discrete power MOSFET as the output device enables this modified Wilson current mirror to control considerable power. The ratio of the emitter degeneration resistors R3/R2 defines the current ratio. This degeneration makes the V_BE matching of Q2 and Q3 relatively non-critical, but the device types have been chosen so that V_BE is similar at the 1:10 design current ratio, improving linearity and temperature stability. The use of complementary mirrors of this type would allow the Fig. 1a VCCS to be extended to higher output power.

Fig. 2. N-type 1:10 ratio mirror.

At I_OUT = 10 mA compliance range is 5 V to 1.5 kV, with current capability limited by Q1 power dissipation (about 30 W). R2, R3 0.1%

P-type high voltage mirror

Fig. 3 is a positive current mirror with a 1:1 current ratio. The structure is similar to Fig. 2, but the low-voltage Q8 is cascoded with a series string of two Darlington-connected pairs, Q6/Q7 and Q9/Q10. As well as increasing the compliance range to 1 kV, this also greatly increases the output impedance. The D2, R7, R8 bias string is returned to the Q4/Q5 mirror, so it does not shunt the output impedance. Note that the overall VCCS output impedance is shunted by the P-mirror impedance divided by the 1:n current gain. The capacitors improve the large-signal response, and R9 together with Q8's C_GD compensate the local feedback.

Fig. 3. P-type 1:1 mirror.

At I_OUT = 1 mA compliance range is −12 V to −1 kV, continuous power dissipation about 2 W. R5, R6 0.1%

Cascode operational amplifier

Fig. 4 shows how a low-voltage OA can be used for U1. The supply currents are relayed to the current mirrors by cascode series stacks of Darlington pairs. U1's no-load supply current (multiplied by the 1:n mirror current gain) sets the quiescent current in the output stage. R20 sets the Fig. 1b VCCS gain at n mA/V. At high supply voltages the need to limit quiescent power dissipation forces the use of a low-supply-current OA with correspondingly low bandwidth. Depending on U1, this may limit the bandwidth and slew rate of the Fig. 1b composite amplifier.

Fig. 4. Cascoded operational amplifier.

20 V < HV+ < 0.8 kV, −1 kV < HV− < −20 V, continuous power dissipation (either rail) about 2 W. U1 = LT1351 (250 μA supply current, 3 MHz bandwidth, 200 V/μs slew rate).

Experimental results

Table 1 summarizes performance characteristics of the N-type (Fig. 2) and the P-type (Fig. 3) mirrors, and of the overall VCCS (Fig. 1b, composed of both types of mirrors and the Fig. 4 cascoded OA). The DC output impedances of these sources do not depend on device matching, and are so high that at frequencies above a few Hz the output can be regarded as being purely capacitive. The slew rate of the mirrors increases with I_OUT, giving a large-signal step response that is roughly independent of amplitude. The small-signal −3 dB bandwidth of the mirrors is strongly dependent on the bias current (set by U1's 0.25 mA supply current). U1's supply current increases during rapid slewing, so the full power −3 dB bandwidth exceeds the small-signal bandwidth. The performance of the overall VCCS is largely determined by the two parallel N-type mirrors. Noise was measured in a 0.1 Hz to 1 kHz bandwidth.

Table 1.

PERFORMANCE TEST RESULTS

	N-type (Fig. 2)	P-type (Fig. 3)	Overall (Fig. 1b)
Impedance (GΩ)	>2 ∥	16 ∥	0.49 ∥
(PF)	65	1.2	170
Rise/fall time (ns)	300/600	40/150	250/600
@ start lOUT(mA),	−2.5	0.25	−25
Step to IOUT (mA)	−25	2.5	25
Bandwidth (kHz)	270	800	280
Noise (nA RMS)	6	--	10
@ IOUT (DC mA)	−2.5	0.25	0

The simplicity of the Fig. 1b open-loop current-summing architecture is attractive, but overall accuracy depends on the component sources. The primary error of these sources is offset current, which may reach a few percent of full scale. Drift of this offset current exceeds the error from finite DC output impedance over intervals as short as a minute. The high VCCS output impedance creates a nearly infinite DC voltage gain when driving a capacitive load such as a piezoelectric actuator, requiring an outer feedback loop that adjusts the current command to keep the output voltage inside the compliance range. This feedback, which is needed in any case to null leakage currents, also nulls VCCS offset current. The VCCS linearity depends on the linearity and matching of the mirrors, but the tested sources were constructed without trims or matched devices. At 100 Hz, with a 20 mA peak-to-peak output, the Total Harmonic Distortion (THD) of the VCCS was 0.8%. Offset current and linearity may be improved considerably by trimming R2 (Fig. 2, both instances).

This design has been successfully used for piezoelectric charge control in a hand-tremor cancellation system [4]. In simulation the VCCS also performs well with a 1:100 current ratio, allowing higher output currents to be achieved.

Conclusion

The high output impedance and low distortion of this current-mirror VCCS are noteworthy considering the use of unmatched discrete devices and the lack of any overall feedback. These characteristics, as well as the high control bandwidth, are a consequence of the high performance of the power MOSFET current mirror. Although a simple adaptation of the Wilson mirror, this in itself appears to be a valuable building block as a high-voltage controlled current source or sink.