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. 2011 Jan 12;11(1):696–718. doi: 10.3390/s110100696

Figure 12.

Figure 12.

(a) Schematic showing the “electronic-first and photonic-last” integration approach for monolithically fabricating the Ge p-i-n photodetector and Si CMOS circuit on common SOI platform. (b) Comparable threshold voltages were observed in both n-MOS and p-MOS transistors despite the introduction of an additional thermal budget during the Ge epitaxy growth. From [75].