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. 2012 Feb 16;8(2):e1002382. doi: 10.1371/journal.pcbi.1002382

Figure 1. Reference Experiment.

Figure 1

Upper panel: A left or right offset vernier was presented for 10 ms followed by a variable blank background (ISI, here shown for 20 ms) and, then, by a second vernier for 10 ms. Lower panel: Observers were asked to indicate whether the first or second vernier was offset to the right. Performance improves quickly with increasing ISI, reaching ceiling performance at 50 ms.