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. Author manuscript; available in PMC: 2012 Mar 5.
Published in final edited form as: IEEE Trans Compon Packaging Manuf Technol. 2011 Dec 1;1(12):1996–2004. doi: 10.1109/TCPMT.2011.2166395

TABLE I.

Test results of bare and integrated dies at Vdd = 5V

pbias pcas ncas nbias
Unpackaged chip (V) 3.648 3.197 1.844 1.383
MOSIS Packaged chip (V) 3.648 3.215 1.826 1.376
Integrated die meas. 1 (V) 3.547 3.124 1.846 1.374
Integrated die meas. 2 (V) 3.542 3.129 1.841 1.378
Integrated die meas. 3 (V) 3.544 3.128 1.842 1.371
Integrated die meas. avg. (V) 3.544 3.127 1.843 1.374
Supply current (mA) 10.00 10.00 10.00 10.00
Trace resistance (Ω) 8.00 8.00 8.00 8.00
Supply IR drop (V) 0.08 0.08 0.08 0.08
Effective bias (V) 3.624 3.207 1.843 1.374
Difference voltage (V) (Bare die vs. Integrated die) 0.024 −0.010 0.001 0.009