Table 3.
Hardware resource consumption of the SOPC system using proposed GHA architecture as hardware accelerator for vector dimensions m = 16 × 16 and m = 32 × 32.
| p | Proposed SOPC with m = 16 × 16 | Proposed SOPC with m = 32 × 32 | |||||
|---|---|---|---|---|---|---|---|
|
|
|
||||||
| LEs | Memory Bits | Embedded Multipliers | LEs | Memory Bits | Embedded Multipliers | ||
| 3 | 44, 377/149, 760 | 446, 824/6, 635, 520 | 708/720 | 94, 736/149, 760 | 453, 992/6, 635, 520 | 708/720 | |
| 4 | 46, 786/149, 760 | 446, 824/6, 635, 520 | 708/720 | 103, 968/149, 760 | 453, 992/6, 635, 520 | 708/720 | |
| 5 | 49, 096/149, 760 | 453, 992/6, 635, 520 | 708/720 | 113, 207/149, 760 | 453, 992/6, 635, 520 | 708/720 | |
| 6 | 51, 449/149, 760 | 453, 992/6, 635, 520 | 708/720 | 122, 537/149, 760 | 453, 992/6, 635, 520 | 708/720 | |
| 7 | 54, 055/149, 760 | 453, 992/6, 635, 520 | 708/720 | 131, 779/149, 760 | 453, 992/6, 635, 520 | 708/720 | |