Table 5.

Computation Time of Various GHA Architectures.

Architectures	Proposed Architecture	[18]	[19]
Vector Dimension m	16 × 16	4 × 4	16 × 8
# of Principal Components p	16	4	16
FPGA Device	Altera Cyclone III EP3C120F780C8	Altera Cyclone III EP3C120F780C8	Xilinx Virtex 4 XC4VFX12
Clock Rate	100 MHz	75 MHz	136.243 MHz
Iteration Numbers	100	100	100
# of Training Vectors per Iteration	888 × 8	888 × 8	888 × 8
Computation Time	1.369 s	86.58 ms	2.09 s