Figure 2.

Schematic drawing of local hardware synapses which are consecutively processed by a global weight update controller. Analog circuits are highlighted in red (with solid frame) and digital circuits in green (dashed frames). The spike-timing-dependence (here one standard spike pair (SSP) with Δt_s, see text) between the pre- and postsynaptic neuron is (a) measured (here a_SSP) and (b) accumulated (here to a_c in case of a causal spike pair, a_a for anti-causal spike pairs is not affected). Then, the global weight update controller evaluates the accumulated spike-timing-dependence by means of a crossed threshold a_th (here a_c > a_th) and modifies the digital weight of the hardware synapse accordingly. The new synaptic weight w_n + 1 is retrieved from the LUT according to the accumulated spike-timing-dependence and the current weight w_n and is written back to the hardware synapse. The analog measurement and accumulation circuit is furthermore minimized by using the reduced symmetric nearest-neighbor spike pairing scheme (Morrison et al., 2008): instead of considering all past and future spikes (all-to-all spike pairing scheme), only the latest and the following spike at both terminals of the synapse are taken into account.