Table 5.
Possible design modifications of hardware synapses, their reduction in terms of required chip resources and their effects on STDP.
| Modification | Resource reduction | Effect on STDP |
|---|---|---|
| Global weight update controller | +++ | Latency between synapse processings; spike pair accumulations necessary |
| Analog measurement of spike-timing-dependence | ++ | Analog measurements are affected by production imperfections |
| Reduced spike pairing scheme | ++ | n.a. |
| Decreased weight resolution | ++ | Loss in synapse dynamics and competition; large weight steps require spike pair accumulations |
| Operation frequency vc of the weight update controller (overall frequency could be increased by implementing multiple controllers) | ++ | Threshold over-shootings distorts synchrony detection |
| Common reset line | + | No synchrony detection possible |
| LUTs (compared to arithmetic operations) | + | None |
| ADCs as compensation for common resets | − | No significant compensation in case of 4-bit synapses |
These modifications are listed by their resource reduction in descending order inspired by the FACETS wafer-scale hardware system and its production process. A larger reduction of chip resources allows more synapses on a single chip.