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. 2010 Aug 4;18(17):17841–17858. doi: 10.1364/OE.18.017841

Fig. 6.

Fig. 6

Architecture of the FPGA integrated solution. A/D and D/A share the same pixel clock which is generated by FPGA, allowing the stimulus location to be accurately registered to the raw video input. The programmability of the FPGA also allows dynamic control of video buffering to minimize prediction latency as the scan approaches the estimated stimulus location.