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. Author manuscript; available in PMC: 2012 Dec 7.
Published in final edited form as: Small. 2010 May 21;6(10):1077–1081. doi: 10.1002/smll.200901198

Figure 3.

Figure 3

MA-PPL printed dot arrays on metallic, insulating, and semiconducting surfaces. a, A 3×3 dot array of PEG-Fe3O4 MNP ink patterned by MA-PPL on an Au substrate by intentionally varying the dwell time (1, 3 and 10s). b, A 3×3 dot array of PEG-Fe3O4 MNP ink patterned by MA-PPL on a Si/SiOx substrate by varying the dwell time (1, 3 and 10s). c, A 3a3 dot array of PEG-Fe3O4 MNP ink patterned by MA-PPL on a GaAs substrate by intentionally varying the dwell time (1, 3 and 10s).