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. Author manuscript; available in PMC: 2013 Sep 28.
Published in final edited form as: Nanotechnology. 2012 Sep 5;23(38):385308. doi: 10.1088/0957-4484/23/38/385308

Figure 1.

Figure 1

Schematic of the nanopore array fabrication process. Low Pressure CVD (LPCVD) process was employed to deposit a low-stress nitride layer above the bulk silicon substrate. A free-standing SiN membrane is fabricated using photolithography. Nanopore arrays were drilled through the SiN membrane using FIB milling. The pore size was measured using TEM. Reduction of the nanopore diameters to sub-10 nm range was achieved using ALD.

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