Table 1.

List of analog current and voltage parameters as well as digital configuration bits.

Scope	Name	Type	Description
Neuron circuits (A)	n/a	in	Two digital configuration bits activating the neuron and readout of its membrane voltage
	gl	in	Bias current for neuron leakage circuit
	τrefrac	in	Bias current controlling neuron refractory time
	El	sn	Leakage reversal potential
	Einh	sn	Inhibitory reversal potential
	Eexc	sn	Excitatory reversal potential
	Vth	sn	Firing threshold voltage
	Vreset	sn	Reset potential
Synapse line drivers (B)	n/a	il	Two digital configuration bits selecting input of line driver
	n/a	il	Two digital configuration bits setting line excitatory or inhibitory
	trise, tfall	il	Two bias currents for rising and falling slew rate of presynaptic voltage ramp
	$g_i^{\max }$	il	Bias current controlling maximum voltage of presynaptic voltage ramp
Synapses (B)	w	is	4-Bit weight of each individual synapse
STP related (C)	n/a	il	Two digital configuration bits selecting short-term depression or facilitation
	USE	il	Two digital configuration bits tuning synaptic efficacy for STP
	n/a	sl	Bias voltage controlling spike driver pulse length
	τrec, τfacil	sl	Voltage controlling STP time constant
	I	sl	Short-term facilitation reference voltage
	R	sl	Short-term capacitor high potential
STDP related (D)	n/a	il	Bias current controlling delay for presynaptic correlation pulse (for calibration purposes)
	A±	sl	Two voltages dimensioning charge accumulation per (anti-)causal correlation measurement
	n/a	sl	Two threshold voltages for detection of relevant (anti-)causal correlation
	τSTDP	g	Voltage controlling STDP time constants

For each hardware parameter the corresponding model parameter names are listed, excluding technical parameters that are only relevant for correctly biasing analog support circuitry or controlling digital chip functionality. Electronic parameters that have no direct translation to model parameters are denoted n/a. The membrane capacitance is fixed and identical for all neuron circuits (C_m = 0.2 nF in biological value domain). Parameter types: (i) controllable for each corresponding circuit: 192 for neuron circuits (denoted with subscript n), 256 for synapse line drivers (denoted with subscript l), 49,152 for synapses (denoted with subscript s), (s) two values, shared for all even/odd neuron circuits or synapse line drivers, respectively, (g) global, one value for all corresponding circuits on the chip. All numbers refer to circuits associated to one synapse array and are doubled for the whole chip. For technical reasons, the current revision of the chip only allows usage of one synapse array of the chip. Therefore, all experiments presented in this paper are limited to a maximum of 192 neurons. For parameters denoted by (A) see equation (1) and Schemmel et al. (2006), for (B), see Figure 1, equation (2), and Dayan and Abbott (2001), for (C) see Schemmel et al. (2007), and for (D) see Schemmel et al. (2006) and Pfeil et al. (2012).