TABLE II.
CMUT in CMOS | Interleaved | Flip Chip | CMUT on CMOS | |
---|---|---|---|---|
Number of Processing Steps |
+ | + | − | − |
Active CMUT Area Optimization | − | − | + | + |
Processing Temperature | n/a | − | + | − |
Gap Height Control | − | + | + | + |
CMUT to CMOS Interconnect Assembly | + | + | − | + |
Foundry Compatibility | + | − | n/a | n/a |