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. Author manuscript; available in PMC: 2013 Aug 21.

Published in final edited form as: IEEE J Solid-State Circuits. 2008 Nov 21;43(11):2546–2557. doi: 10.1109/JSSC.2008.2005818

TABLE I.

Prototype performance summary

Chip	Technology	0.35-μm high-voltage CMOS
	Area	16 mm²
	Resolution	64-×-64 pixels
	Pitch	40 μm
	Supply Voltage	4.0 V
	Current Consumption	350 mA

TDC	LSB	350 ps
	Jitter	<1 LSB
	INL	1.37 LSB
	DNL	1.04 LSB

SPAD	DCR	1059 Hz
	Maximum PDP	4.7%
	at Wavelength	440 nm

Array	GW Measurement Rate	1144 measurements/s
	TCSPC Measurement Rate	718 measurements/s
	Maximum Frame-rate	3.9 Hz