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. Author manuscript; available in PMC: 2013 Sep 3.
Published in final edited form as: IEEE Trans Ultrason Ferroelectr Freq Control. 2012 Oct;59(10):2201–2209. doi: 10.1109/TUFFC.2012.2446

TABLE II.

Resource Utilization of the Field-Programmable Gate Array (FPGA).

Article Resource utilization
Adaptive look-up tables (ALUTs) 4855 (10%)
Pins 216 (44%)
DSP block 9-bit elements 64 (22%)
Memory bits 53152 (2%)
PLLs 2 (33%)

DSP = digital signal processing; PLL = phase-locked loop.