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. Author manuscript; available in PMC: 2014 Oct 7.
Published in final edited form as: Lab Chip. 2013 Oct 7;13(19):3929–3934. doi: 10.1039/c3lc50437a

Fig. 3.

Fig. 3

Surface profile over the chip-carrier joint area. (A) 3D image of the CMOS chip and die carrier separated by a trench; (B) linear scan profile at location of arrow in (A) with x-axis scale roughly 10× the y-axis scale to highlight vertical features.