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. Author manuscript; available in PMC: 2013 Oct 23.
Published in final edited form as: IEEE Trans Circuits Syst I Regul Pap. 2013 Jan 9;60(6):1407–1418. doi: 10.1109/TCSI.2012.2220464

Fig. 3.

Fig. 3

Loop delay induced sampling noise in fixed window level crossing ADC. The previous pulse ends at TO, the current pulse starts at T1’ and finishes at T2. T1 to T1’ is the propagation delay of the comparator. The input signal between T1 and T2 will be lost. The amplitude between S and Sr is the sampling noise. The sampling noise can be partially compensated in the digital domain by estimating the slope of the input signal using extrapolation from the previous pulse, as shown as Sc. The sampling error can be reduced by implementing delta modulator with shorter loop delay.