TABLE II.
Year | 2012 | 2008 | 2011 | 2006 | 2010 |
---|---|---|---|---|---|
Integrated Circuit Technology | 0.5µm CMOS | 90nm CMOS | 0.18µm CMOS not fully integrated | 0.6µm CMOS simulation | 0.13µm CMOS |
Power Supply | 3.3V | IV | 0.7V | 5V | 1.2V |
ADC Area | 0.06mm2 | 0.06mm2 | 0.96mm2 | N/A | 0.17mm2 |
ADC Method | Fixed Window Asynchronous | Floating Window Asynchronous | Floating Window Asynchronous | Integration Asynchronous | SAR ADC Clocked |
Input Signal Bandwidth | 0.2–5kHz | 0.2–3.4kHz (Audio) | 1kHz (full scale) | 5.4kHz | N/A |
Measured SNDR | 31dB | 50 dB | 43.2 dB | N/A | 39.32dB |
Power Consumption | 8.25µW (Static) 106µW (1kHz Input) |
45µW (ADC only) |
25µW w/o off chip logic |
100 µW simulation | 1µW |
Conversion Rate (per second) | 60k | 512ka | 50k | 10k | |
Figure of Merit (l/nj · mm2) | 662bc | 1,048,646c | 601bcd | N/A | 5379e |
Reference | This Work | [39] | [23] | [15] | [9] |
Level crossing sampling with 8bit resolution for 1kHz input signal
Using off-line reconstruction
SNDR is set to 1kHz input signal
Digital logic feedback not integrated on chip
Using clocked ADC, no data compression