Table 10.
Comparisons of the proposed GHA circuit with other FPGA-based feature extraction implementations. LE, logic element.
| Arch. |
FPGA Devices |
Logic Cells or LEs |
DSPelements or Multipliers |
Embedded Bits |
Maximum Clock Rate |
Throughput |
|---|---|---|---|---|---|---|
| Proposed GHA Arch. |
Altera Cyclone IV EP4CGX150 |
15,688 | 128 | 63,488 | 1 GHz | 4.50 × 107 |
| GHA Arch. in [12] |
Xilinx Virtex 6 XC6VSX315T |
12,610 | 12 | 0 | 100 MHz | 1.60 × 106 |
| GHA Arch. in [30] |
Xilinx Cyclone IV EP4CGX150 |
9,144 | 432 | 63,448 | 50 MHz | 2.75 × 106 |