Table 11.

Comparisons of the proposed FCM circuit with other FPGA-based clustering implementations.

Arch.	FPGA Devices	Logic Cells or LEs	DSP elements or Multipliers	Embedded Bits	Maximum Clock Rate	Throughput
Proposed FCM Arch.	Altera Cyclone IV EP4CGX150	4,468	23	113,520	1 GHz	3.38 × 107
FCM Arch. in [20]	Altera ACEX 1K EP1K100FC484	4,205	0	24,576	NA	3.28 ×106