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. 2013 Nov 1;13(11):14860–14887. doi: 10.3390/s131114860

Table 7.

The training time of the proposed spike sorting system for various clock rates.

Implementation SOC- Based
Spike Sorting
Software
Spike Sorting
Processor Altera NIOS II Intel I7
Clock Rate 1 MHz 10 MHz 50 MHz 200 MHz 800 MHz 1 GHz 2.61 GHz

GHA (ms) 1,776.51 177.81 35.60 8.92 2.23 1.78 181.38
FCM (ms) 204.33 20.60 4.17 1.05 0.26 0.21 11.80
Total (ms) 1,980.84 198.4 39.77 9.97 2.49 1.99 193.18