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. Author manuscript; available in PMC: 2014 Feb 24.
Published in final edited form as: IEEE Trans Biomed Circuits Syst. 2013 Jun;7(3):213–224. doi: 10.1109/TBCAS.2012.2198649

Fig. 9.

Fig. 9

Fabricated chip micrograph and floor plan of the active voltage doubler in ON-Semi 0.5-μm Std. CMOS process, occupying an area of 0.144 mm2.