Table 2.

A comparison of this work with [4].

	Maximum efficiency approach (this work)	Maximum efficiency approach [4]
Number of stages	5	10
Transistor W/L	30 μm/0.18 μm	30.2 μm/0.5 μm
Output voltage	1.15 V at −8 dBm 50 Ω input power	1.05 V at −8 dBm 50 Ω input power
Capacitor per stage	32 pF/stage (160 pF total)	5.6 pF/stage (56 pF total)
Efficiency at 220 mV Vin and 200 K output load	40.17%	33.69%
Additional requirement	Deep n-well	Zero-Vth native transistor