. 2014 Mar 31;8:48. doi: 10.3389/fnins.2014.00048
Copyright © 2014 Camuñas-Mesa, Serrano-Gotarredona, Ieng, Benosman and Linares-Barranco.
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Figure 7.
Block diagram for a sample network with 3 × 3 convolutional blocks implemented on FPGA.