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. Author manuscript; available in PMC: 2014 May 1.
Published in final edited form as: Lab Chip. 2012 Jul 5;12(17):3159–3167. doi: 10.1039/c2lc40109f

Fig. 4.

Fig. 4

Predicted and measured results for interception efficiencies of post arrays: (a) schematic model streamlines for w/dc = 5; (b) model streamlines for w/dc = 1; (c) model streamlines for w/dc = 0.2; (d) predicted and measured interception efficiencies for different array spacings, with dp/dc = 0.02; (e) predicted and measured interception efficiencies for different array spacings, with dp/dc = 0.1.