Figure 2. C–V characteristics of the devices.

(a) C–V data for all samples in the HRS, plotted as C⁻² versus V. The lines are fits to Equation (6). The inset shows the equivalent circuit model and the voltage partitioning between the depletion and interface layer capacitances, C_d and C_i. (b) Extracted built-in potentials V_bi and depletion widths W_D at zero bias. (c) Ratio between the currents in LRS and HRS as the function of voltage (top) and the calculated depletion width under forward bias (bottom).