Table 10.

Comparison of various neuromorphic ADC concepts.

References	Description	Most similar conventional architecture	Parallel/ serial	Required analog precision / required design effort	Config.	Power	Sensor fusion possible
This work	digital decoding of analog input from neuron population signals	Flash and feedforward oversampling	Parallel	Very low / low, repetitive neuron circuit	Rate and resolution	x10 more power than best reported conventional	Yes
Tapson and van Schaik, 2012	Parallel noise shaping network with lateral inhibition	DSM	Parallel	Low / low, repetitive neuron circuit	rate and resolution	No data	No data
Chande and Poonacha, 1995	Binary threshold neurons in a weighted MSB to LSB decoder network	Successive approximation	Serial	Equal to ADC resolution / low, repetitive neuron circuit	resolution	No data, but likely comparable to median conventional	Yes
Yang and Sarpeshkar, 2006	Time-domain pipeline architecture, with neurons handling time domain processing	Pipeline	Serial	Equal to ADC resolution / high, numerous handcrafted components	No	on par with best reported conventional, subthreshold operation	No