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. Author manuscript; available in PMC: 2015 Jul 21.
Published in final edited form as: Lab Chip. 2014 Jul 21;14(14):2469–2479. doi: 10.1039/c4lc00193a

Fig. 6.

Fig. 6

Simulation of parasitic capacitance for two different substrates. Geometry used for the simulation for glass substrate (a) and SOI substrate (d). Variation of parasitic capacitance as a function of (b), (e) electrode separation and (c), (f) electrode width for glass and SOI substrate respectively.