Table 2.
Configurations of target CPU micro architectures used for the experiments
| CPU | Intel Atom | Intel Xeon Westmere |
|---|---|---|
| Clock | 2.13 GHz | 3.40 GHz |
| L1I cache | 32 KB | 32 KB |
| L1D cache | 24 KB | 32 KB |
| L2 cache | 512 KB | 256 KB |
| L3 cache | N/A | 8 MB |
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