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. 2014 Sep 16;14(9):17192–17211. doi: 10.3390/s140917192

Figure 7.

Figure 7.

(a) (A) Chip microphotograph of Version 1 chip (individual blocks are not visible due to the top-metal dummy structure) and (B) layout with omitted top metal layer. Test structures: (B1) readout circuit, (B2) bandgap, (B3) PTAT, (B4) biasing stage, (B5) relaxation oscillator, (B6) comparator. (b) Chip microphotograph of Version 2 chip with smaller sensing capacitor: (I) readout circuit, (II) capacitive sensing element.