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. Author manuscript; available in PMC: 2014 Dec 1.
Published in final edited form as: Nat Mater. 2012 Dec 16;12(3):246–252. doi: 10.1038/nmat3518

Figure 3. Room temperature electrical properties of the vertical and planar transistors.

Figure 3

a, Isd-Vsd output characteristics of a vertical transistor. The current is normalized by the area. b, Isd-Vgs transfer characteristics of the device shown in a at Vsd = −0.1, −0.2, and −0.5 V. c, Isd-Vsd output characteristics of a planar transistor with MoS2 channel between a graphene electrode and metal electrode. d, Ids-Vsd output characteristics of a planar transistor with two top metal electrodes on planar MoS2 channel. The current is normalized by the width of the electrode in c and d. The back-gate voltage is varied from −80 V to 0 V in the step of 20 V in a, c and d. Insets in a, c and d shows the schematics of the transistor structure for each output characteristics.