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. 2014 Nov 17;14(11):21603–21625. doi: 10.3390/s141121603

Figure 3.

Figure 3.

Timing diagram of the proposed two-step SS ADC. Waveforms of (a) the IN1+ and IN1− terminals of the comparator; (b) the differential voltages VR and Vsig; (c) the comparator output.