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. 2015 Feb 23;9(1):014125. doi: 10.1063/1.4913497

FIG. 2.

FIG. 2.

3D πDEP device fabrication process flow. (a) Top view of DRIE lag mask design. (b) Pattern oxide mask and then use RIE lag 3D silicon etch. (c) Remove oxide lattice structure with BOE. (d) Anodically bond silicon to Pyrex wafer under vacuum. (e) Melt Pyrex into silicon mold. (f) Etch all silicon with KOH. (g) Pour PDMS over Pyrex master and cure. (h) Remove PDMS from glass master and punch ports. (i) Plasma bond to glass slide. (j) Evaporate electrodes on separate glass substrate. (k) Align electrodes and microfluidic device prior to experimental runs.