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. 2015 Mar 2;9:51. doi: 10.3389/fnins.2015.00051

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Copyright © 2015 Saïghi, Mayr, Serrano-Gotarredona, Schmidt, Lecerf, Tomas, Grollier, Boyn, Vincent, Querlioz, La Barbera, Alibart, Vuillaume, Bichler, Gamrat and Linares-Barranco.

This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) or licensor are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.

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(A) Optical microscope image of the chip after patterning showing 5×10 ferroelectric tunnel junctions (FTJ); (B) 3D representation of a zoomed area containing a few FTJs. The three parallel bars are the ground-signal-ground contact pads; (C) 3D sketch of one FTJ (Boyn et al., 2014); (D) schema of the voltages applied to the memristor. The reading pulse V_read is lower than the threshold (V_read = 200 mV). Writing is performed by the application of 100 ns voltage pulses of different amplitudes. The writing voltages increase from −2 V to V_max by a step of 0.1 V. Then, the amplitude of the writing pulses decreases to −V_max; (E) dependence of the resistance of the ferroelectric tunnel memristor measured at V_read on the applied writing cycles. The different curves correspond to different consecutive measurements with varying V_max.