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. 2015 Jun 2;10:249. doi: 10.1186/s11671-015-0958-4

Fig. 5.

Fig. 5

Improved SCE control parameters of DIBL and SS as the gate length scaling for fabricated S-FinFETs. a DIBL and SS are shown as a function of gate length for S-FinFETs and normal FinFETs. Simulated DIBL variations are included. b Simulated electrostatic potential as well as dE x /dx in different channels for explaining the improved DIBL in S-FinFETs