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. Author manuscript; available in PMC: 2015 Jul 1.
Published in final edited form as: IEEE Int Conf Systems Biol. 2014 Oct;2014:176–183. doi: 10.1109/ISB.2014.6990752

Fig. 3.

Fig. 3

An example of a half adder circuit in implementing function fha(x, y) = x + y with x, y ∈ {0, 1}, which includes an XOR gate and an AND gate. The half adder has two single binary inputs x and y and two outputs, i.e., sum (S) and carry (C), where the decimal output can be represented as fha(x, y) = 2C + S. Each logic gate (e.g., XOR or AND gate) has three wires, which correspond to two binary inputs (e.g., W1 and W2 in the XOR gate) and one binary output (e.g., W3 in the XOR gate). The truth tables of the half adder circuit, XOR and AND gates have been shown as references.