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. 2015 Jul 6;5:11921. doi: 10.1038/srep11921

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(a) Cross-sectional schematic of the top-gated devices together with the electrical connections. (b) I_ds – V_tg curves with V_ds ranging from 50 mV to 500 mV. The inset shows the I_ds – V_ds curves with the top gate voltages of 0 V and 2 V. (c) Top gate leakage current of the device. Optical image of the top gate device is attached as the inset of (c). Top gate dielectric of this device is 60 cycles Al₂O₃ deposited with 60 s remote oxygen plasma pretreatment. All these measurements were performed at room temperature with the back gate grounded.