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. 2015 Aug 4;9:97. doi: 10.3389/fncom.2015.00097

Table 2.

Values of the coupling parameters and input stimulation protocols for inputs labeled as “1” in the implementation of the binary logic gates shown in Figure 2.

Parameters Logic gates
AND NAND NOR OR XNOR XOR
αA1A2 2.0 27.0 5.0 2.0 27.0 2.0
βA1A2 8.0 5.0 1.0 8.0 5.0 8.0
pA1(t) (Hz) 250 150 155 250 155 250
pA2(t) (Hz) 250 150 155 250 155 250
δA1 (Hz) 120 150 65 250 250 250
δA2 (Hz) 120 150 65 250 250 250
fA1 (Hz) 10.8 8.5 8.5 8.5 8.5 9.5
fA2 (Hz) 10.8 8.5 8.5 8.5 8.5 8.5
ξA1 (Hz) 0.0 0.0 1000 0.0 1000 0.0
ξA2 (Hz) 0.0 0.0 1000 0.0 1000 0.0