Fig. 5.

Block diagram of the frequency divider design. Each D-flip-flop is used to realize a “divide-by-2” circuit by connecting the output $\overline{Q}$ to its own input D. For example, clock input with a frequency of f₀ is fed into the first flip-flops to generate f₀/2. This f₀/2 is again used to clock the second flip flop and generate f₀/4. The sequence can be extended indefinitely. If implemented on-chip, both circuit area and power consumption will be very small and thus can be powered by a miniature battery.