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. Author manuscript; available in PMC: 2017 Jan 14.
Published in final edited form as: Nanoscale. 2016 Jan 14;8(2):785–795. doi: 10.1039/c5nr04580k

Figure 1.

Figure 1

Schematic illustrating the suggested process to be used for the fabrication of on-chip np-Au (brown) material libraries supported on silicon or glass (blue) using laser-based precise photothermal treatment to selectively anneal each np-Au pattern, resulting in an altered feature size (denoted by color change) on each pattern.