Table 5.
Processing time of the test circuits (in seconds).
| Circuit | Exhaustive | Monte Carlo compared to exhaustive (%) | Proposed method compared to exhaustive (%) |
|---|---|---|---|
| Quad 2-Input multiplexer (TTL) | 52.279635 | 13.2 | 4 |
| Look-Ahead Carry Generator(TTL) | 14.121473 | 53.3 | 31.8 |
| 4-bit binary full adder (TTL) | 46.103831 | 43.68 | 126.5 |
| Quad 2-Input multiplexer (CMOS) | 60.180474 | 12.5 | 4.4 |
| Look-Ahead Carry Generator (CMOS) | 15.671148 | 54.02 | 222.4 |
| 4-bit binary full adder (CMOS) | 41.204726 | 43.5 | 125.2 |
| ISCAS’85 (C17) | 0.037201 | 144.1 | 57.4 |
| Average value | 32.8 | 29.9 | 66.7 |