Fig 1. Schematic diagram of modular distributed computation and the scalability of this architecture in logic circuits.

(A) Schematic diagram of spatially distributed computation. A spatially organized set of chambers defining a set of modules provides a source of modularity by separating different subsets of cells (consortia) into different groups. Each module contains one or more cells from the Input Layer (IL) library (that respond according to an ID or NOT logic), all of which sense only one signal from a given repertoire of N inputs (X) and respond by secreting a communication molecule ω. All modules also include Output Layer (OL) cells that produce the output β implementing a NOT logic, in response to molecule ω. The concentration of β can be quantified directly from the module if the OL is a reporter cell and then the output of the whole circuit (Final output) is the OR combination of each consortium output. Alternatively, the final output can be quantified by using an optional Buffer Layer (BL) cell (BUF) that integrates the final outcome from the different modules if β is a secretable molecule. (B) Schematic diagram explaining the differences between a circuit with a secreted output (upper panel) and transducer circuits (bottom panel). The buffer cell (BUF) collects the output of the different chambers and produces the final computation (top). (C) Illustration of the combinatorial potential of spatially restricted distributed computation architecture. The plot shows the required number of cells, the number of modules and the number of potential N-input logic functions against the number of inputs. Spatial modules (M) and cells number (Z) scale slowly with the number of inputs (N), whereas the repertoire of logic functions shows super exponential increases even for small N.