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. 2016 Jan 28;23(Pt 2):395–403. doi: 10.1107/S1600577515022754

Figure 2.

Figure 2

Each ASIC is divided into eight banks of pixels. Each bank is 129 × 16 pixels with a dedicated analog output for each bank. Rows are addressed in parallel across all banks with bank-wise analog multiplexers at the top of the columns.